1. Field of the Invention
This invention relates generally to a nonvolatile memory and more specifically to a memory architecture for a three volt flash electrically erasable programmable read only memory.
2. Description of Related Art
Flash EEPROMs (electrically erasable programmable read only memory) are nonvolatile memory devices that are gaining widespread use in the computer industry. The operation and structure of one flash EEPROM is discussed in U.S. Pat. No. 4,698,787 issued on Oct. 6, 1987, to Mukherjee et al., which is incorporated herein by reference in its entirety. Another discussion of the operation and structure of a flash EEPROM, which is also incorporated herein by reference in its entirety, is Gheroge Samashisa, et al., "A 128K Flash EEPROM Using Double-Polysilicon Technology," IEEE Journal of Solid State Circuits, Vol. SC-22, No. 5, BP 676-83, October, 1987.
Flash EEPROMs provide many advantages over other nonvolatile memory devices. One particularly advantageous flash EEPROM array is disclosed in U.S. Pat. No. 5,077,691, entitled "Flash EEPROM Array With Negative Gate Voltage Erase Operation," of S. Haddad et al , issued on Dec. 31, 1991 ("the '691 patent").
FIG. 1 is a block diagram of the architecture disclosed in the '691 patent. An array 100 of flash EEPROM cells 101 has a plurality of bit lines BL-0 to BL-n and a plurality of word lines WL-0 to WL-m. Each flash EEPROM cell 101, which may be either a symmetric cell or an asymmetric cell, includes a control gate 103 that is connected to a word line WL, a floating gate, a source S that is tied to the source of each cell in array 100, and a drain D that is connected to a bit line BL.
As used herein, "a symmetric cell" 200 has a source region 201 and a drain region 202, which are formed using the same process steps, and which are laid-out symmetrically about a vertical line drawn 205 through the center of the control gate 203 in a cross-sectional cut of the cell. An "asymmetric cell" also has a source and a drain region, but an additional process step or steps have been used to form one of the source and drain regions so that the source and drain regions are no longer laid-out symmetrically about a vertical line drawn 205 through the center of the control gate 203 in a cross-sectional cut of the cell.
As is known to those skilled in the art, the integrated circuit containing flash EEPROM array 100 includes buffers, sense amplifiers, and column and row address circuitry. In FIG. 1, only the switching mechanisms 121, 111 that provide various voltage sources to bit lines BL-0 to BL-n and word lines WL-0 to WL-m are illustrated.
Table 1 gives voltage V.sub.G, which is applied to gate 103, voltage V.sub.D, which is applied to drain D, and voltage V.sub.S, which is supplied to source S, for reading, programming and erasing of each cell 101 in array 100. Voltage V.sub.S was varied in a positive range from above zero to voltage V.sub.CC, typically 0.5 volts to +5 volts and usually in the range of +4 volts to +6 volts. Power supply voltage V.sub.CC was +5 volts.
TABLE 1 ______________________________________ Operation Mode V.sub.G V.sub.D V.sub.S ______________________________________ Read V.sub.CC +1.0 V to +2.0 V 0 V Cell +12 V +6 V 0 V Programming Program 0 V +6 V or 0 V 0 V Inhibit of Row Program +12 V or 0 V 0 V 0 V Inhibit of Column Erase -10.5 V Float 5 V Erase 0 V to V.sub.S Float 0 V to V.sub.S Inhibit of Row ______________________________________
Herein, "V" is used to represent "volts" while a "V" with a subscript represents either a particular voltage level or a particular voltage supply.
The programming of flash EEPROM cells 101 was accomplished by hot electron injection into the floating gate while erasure via gate 103 with a negative voltage depended upon Fowler Nordheim tunneling. Negative voltage gate erasure provided many advantages, which are discussed in U.S. Pat. No. 5,126,808 entitled "Flash EEPROM Array With Paged Erase Architecture," of A. J. Montalvo and M. A. Van Buskirk issued on Jun. 30, 1992, and the '691 patent, both of which are incorporated herein by reference in their entirety.
A common problem with flash EEPROM array 100, which limits the functionality of array 100, is the bit overerasure phenomenon. If an unprogrammed flash EEPROM cell is repeatedly erased, the floating gate may acquire a positive charge such that a positive potential is created in the floating gate. This positive charge may form a channel region even though no voltage is applied to the control gate.
When the positive potential on the floating gate was sufficient to turn on the flash EEPROM cell, sometimes referred to as "cell", the overerasure prevented reading of any other cell in the array column containing the overerased cell due to leakage current from the unselected overerased cell(s). Consequently, flash EEPROM arrays with an overerased cell were considered inoperative. Typically, either the flash EEPROM array was replaced or the column with the overerased cell was isolated from the array and the array was repaired with redundant cells included in the integrated circuit.
Another short coming of flash EEPROM array 100 is that as the control gate voltage used in a read becomes lower the conductance of memory array cell 101 becomes less. More specifically, the conductance reduces at least linearly with the reduction in the control gate voltage. The resulting reduction in current results in a slower bit line capacitance discharge time assuming that the bit line capacitance is not reduced proportionately with the current reduction. The slower bit line discharge time results in slower access time performance of the memory array.
As computers become smaller, the power supply voltage is dropping to about three volts while the speed is increasing. Therefore, the current flash EEPROM architectures are not suitable for use in such computers because the performance of the flash EEPROM degrades the performance of the computer. Unfortunately with continued scaling of the flash EEPROM cell, the channel implant concentration is generally increased. The increased concentration increases the threshold voltage of the cell. This increase in threshold voltage further reduces the current sinking capability of flash EEPROM cell 101. In summary, the limitations introduced by the threshold voltage coupled with the overerasure problems appear to limit the use of flash EEPROMs at low voltages and high speed.